1. Field of the Invention
The present invention relates to semiconductor memory devices and particular to configurations of a memory cell select circuit and those of a redundant circuit thereof.
2. Description of the Background Art
In recent years, as microprocessors (MPUs) are improved in operating speed, there has been used synchronous DRAM (SDRAM) operating in synchronization with a clock signal to achieve rapid access e.g. of a dynamic random access memory (DRAM) used as a main memory device.
Internal operation of such an SDRAM and the like is divided into row- and column-related operations for control.
The SDRAM and the like also employ a bank configuration, the memory cell array divided into banks each capable of independent operation, to achieve further rapid operation. More specifically, for each bank, the operation is controlled independently with respect to the row- and column-related operations.
Typically, a word line is hierarchically configured by main and subordinate word lines to reduce the load to be driven by a drive circuit to provide for rapid operation in the operation of selecting a row of the memory cell array or a word line in the row-related operation.
In semiconductor memory devices such as an SDRAM and the like having a conventional multibank configuration, however, the hierarchical configuration described above disadvantageously results in an increased number of the elements required for selecting a subordinate word line.
Furthermore, in recent years a memory circuit and a logic circuit are integrated on a single chip to provide e.g. chips on which a DRAM and a logic circuit are mounted mixedly for the purpose of achieving multifunction, improving data processing speed and the like. For this type of chips, the data bus width for communicating data between a storage device such as a DRAM and a logic circuit that are integrated on a single chip, i.e., the number of bits of data communicated at one time, tends to be increased to provide rapid process.
Furthermore, an input/output line (an I/O line pair) transmitting data read from a memory cell to an interface circuit is often configured hierarchically in view of enhancement of operating speed and the like. To transmit data from a memory cell via the hierarchical I/O line pair, a gate circuit is provided therebetween for selectively connecting a bit line pair connected to the memory cell selected in a read operation and the I/O line pair communicating the data. For multibank, memory cell arrays, such a gate circuit also tends to be increased in the number of elements used therefor. Particularly, inputting and outputting data on a bus with such a large bus width as described above requires an increased number of independently operable I/O line pairs. This also increases the number of the gate circuits described above and hence the number of elements configuring the gate circuits.